Semiconductor device and method for fabricating the same

ABSTRACT

A plurality of metal interconnects are formed on a lower interlayer insulating film provided on a semiconductor substrate. An upper interlayer insulating film is formed so as to cover the plural metal interconnects. The upper interlayer insulating film has an air gap between the plural metal interconnects, and a top portion of the air gap is positioned at a level higher than the plural metal interconnects.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor device includingmetal interconnects having an air gap and a method for fabricating thesame.

[0002] A semiconductor device including metal interconnects having anair gap and a method for fabricating the same according to a firstconventional example will now be described with reference to FIGS. 11Athrough 11C, 12A through 12C, 13A through 13C and 14A through 14C.

[0003] First, as shown in FIG. 11A, a lower interlayer insulating film11 of an insulating material is formed on a semiconductor substrate 10by chemical vapor deposition (CVD) or spin coating. Thereafter, althoughnot shown in the drawing, a plug connected to the semiconductorsubstrate 10 or an interconnect formed on the semiconductor substrate 10is formed in the lower interlayer insulating film 11.

[0004] Next, a first barrier metal layer 12, a first metal film 13 and asecond barrier metal layer 14 are successively deposited on the lowerinterlayer insulating film 11. The first barrier metal layer 12 and thesecond barrier metal layer 14 are deposited by sputtering, and the firstmetal film 13 is formed by the sputtering, CVD or plating. Thereafter,an insulating film 15 is formed on the second barrier metal layer 14 bythe CVD or spin coating.

[0005] Then, as shown in FIG. 11B, after forming a first resist pattern16 on the insulating film 15 by lithography, the insulating film 15 isdry etched by using the first resist pattern 16 as a mask. Thus, plugopenings 17 are formed in the insulating film 15 as shown in FIG. 11C.

[0006] Next, as shown in FIG. 12A, a second metal film 18 is depositedon the insulating film 15 so as to fill the plug openings 17 by thesputtering, CVD or plating.

[0007] Then, as shown in FIG. 12B, an unnecessary portion of the secondmetal film 18 present on the insulating film 15 is removed by chemicalmechanical polishing (CMP), thereby forming contact plugs 19 from thesecond metal film 18. Thereafter, as shown in FIG. 12C, the insulatingfilm 15 is dry etched so as to reduce the thickness thereof. Thus, upperportions of the contact plugs 19 protrude from the insulating film 15.

[0008] Subsequently, as shown in FIG. 13A, a second resist pattern 20 isformed on the insulating film 15 by the lithography. Then, as shown inFIG. 13B, the insulating film 15 is dry etched by using the secondresist pattern 20 as a mask, thereby forming a patterned insulating film15A in the pattern of interconnects.

[0009] Next, as shown in FIG. 13C, the second barrier metal layer 14,the first metal film 13 and the first barrier metal layer 12 are dryetched by using the second resist pattern 20, the patterned insulatingfilm 15A and the contact plugs 19 as a mask, thereby forming metalinterconnects 21 composed of a patterned second barrier metal layer 14A,a patterned first metal film 13A and a patterned first barrier metallayer 12A. In this manner, a remaining resist 22 in the shape of ridgeswith facets inclined at approximately 45 degrees is formed on thepatterned insulating film 15A and facets are also formed in top portionsof the patterned insulating film 15A.

[0010] In the first conventional example, the metal interconnects 21 areformed by dry etching the second barrier metal layer 14, the first metalfilm 13 and the first barrier metal layer 12 with the second resistpattern 20, the patterned insulating film 15A and the contact plugs 19used as the mask. Instead, the metal interconnects 21 may be formed bydry etching the second barrier metal layer 14, the first metal film 13and the first barrier metal layer 12 with the patterned insulating film15A and the contact plugs 19 used as the mask after removing the secondresist pattern 20 by ashing. In this case, the patterned insulating film15A is sputtered during the dry etching for forming the metalinterconnects 21, and hence, facets are also formed in the top portionsof the patterned insulating film 15A.

[0011] Next, as shown in FIG. 14A, portions of the lower interlayerinsulating film 11 between the metal interconnects 21 are trenched bythe dry etching. Thus, the remaining resist 22 is removed but istransferred to the patterned insulating film 15A, resulting in enlargingthe facets of the patterned insulating film 15A.

[0012] Then, as shown in FIG. 14B, an upper interlayer insulating film23 is formed over the contact plugs 19, the metal interconnects 21 andthe lower interlayer insulating film 11 by the CVD and air gaps 24 areformed in the upper interlayer insulating film 23 between the metalinterconnects 21.

[0013] Subsequently, as shown in FIG. 14C, the upper interlayerinsulating film 23 is planarized by the CMP. Thus, the interconnectshaving the air gaps are completed. Thereafter, the aforementionedsequence is repeated, so as to fabricate a semiconductor device having amulti-layer interconnect structure.

[0014] Since the upper interlayer insulating film 23 is formed with thefacets formed in the top portions of the patterned insulating film 15Ain the first conventional example, the upper interlayer insulating film23 tends to enter the portions between the metal interconnects 21.Therefore, the top portion of the air gap 24 (a portion with atriangular cross-section) is positioned at substantially the same levelas the metal interconnect 21.

[0015] A semiconductor device including metal interconnects having anair gap and a method for fabricating the same according to a secondconventional example will now be described with reference to FIGS. 15Athrough 15C, 16A through 16C, 17A through 17C, 18A and 18B.

[0016] First, as shown in FIG. 15A, a lower interlayer insulating film31 of an insulating material is formed on a semiconductor substrate 30by the CVD or spin coating. Thereafter, although not shown in thedrawing, a plug connected to the semiconductor substrate 30 or aninterconnect formed on the semiconductor substrate 30 is formed in thelower interlayer insulating film 31.

[0017] Next, a first barrier metal layer 32, a first metal film 33 and asecond barrier metal layer 34 are successively deposited on the lowerinterlayer insulating film 31. The first barrier metal layer 32 and thesecond barrier metal layer 34 are deposited by the sputtering, and thefirst metal film 33 is formed by the sputtering, CVD or plating.Thereafter, an insulating film 35 is formed on the second barrier metallayer 34 by the CVD or spin coating.

[0018] Then, after forming a first resist pattern 36 on the insulatingfilm 35 by the lithography as shown in FIG. 15B, the insulating film 35is dry etched by using the first resist pattern 36 as a mask so as toform a patterned insulating film 35A in the pattern of interconnects asshown in FIG. 15C. Thereafter, the first resist pattern 36 is removed bythe ashing.

[0019] Next, as shown in FIG. 16A, the second barrier metal layer 34,the first metal film 33 and the first barrier metal layer 32 are dryetched by using the patterned insulating film 35A as a mask, therebyforming metal interconnects 37 composed of a patterned second barriermetal layer 34A, a patterned first metal film 33A and a patterned firstbarrier metal layer 32A. Thus, the patterned insulating film 35A issputtered during the dry etching for forming the metal interconnects 37,and hence, facets are formed in the top portions of the patternedinsulating film 35A.

[0020] Then, as shown in FIG. 16B, portions of the lower interlayerinsulating film 31 between the metal interconnects 37 are trenched bythe dry etching. Thus, the patterned insulating film 35A is reduced inits thickness with the facets formed in the top portions thereof.

[0021] Subsequently, as shown in FIG. 16C, an upper interlayerinsulating film 38 is formed over the metal interconnects 37 and thelower interlayer insulating film 31 by the CVD and air gaps 39 areformed in the upper interlayer insulating film 38 between the metalinterconnects 37.

[0022] Next, after planarizing the upper interlayer insulating film 38by the CMP as shown in FIG. 17A, a second resist pattern 40 is formed onthe upper interlayer insulating film 38 as shown in FIG. 17B.

[0023] Then, as shown in FIG. 17C, the upper interlayer insulating film38 is dry etched by using the second resist pattern 40 as a mask,thereby forming plug openings 41 in the upper interlayer insulating film38. Thereafter, the second resist pattern 40 is removed by the ashing.

[0024] Subsequently, as shown in FIG. 18A, a second metal film 42 isdeposited on the upper interlayer insulating film 38 by the sputtering,CVD or plating so as to fill the plug openings 41.

[0025] Next, as shown in FIG. 18B, an unnecessary portion of the secondmetal film 42 present on the upper interlayer insulating film 38 isremoved by the CMP, so as to form contact plugs 43 from the second metalfilm 42. Thus, the interconnects having the air gaps are completed.Thereafter, the aforementioned sequence is repeated so as to fabricate asemiconductor device having a multi-layer interconnect structure.

[0026] Since the upper interlayer insulating film 38 is formed with thefacets formed in the top portions of the patterned insulating film 35Ain the second conventional example, the upper interlayer insulating film38 tends to enter the portions between the metal interconnects 37.Therefore, the top portion of the air gap 39 (a portion with atriangular cross-section) is positioned at substantially the same levelas the metal interconnect 37.

[0027] If a potential difference is caused between the adjacent metalinterconnects 21 or 37, an electric field is collected at the upper andlower ends of each metal interconnect 21 or 37. This results in aproblem that the capacitance between the interconnects is increased.

[0028] Therefore, in the first or second conventional example, theportions of the lower interlayer insulating film 11 or 31 between themetal interconnects 21 or 37 are trenched before forming the upperinterlayer insulating film 23 or 38. Thus, the lower ends of the airgaps 24 or 39 are positioned to be lower than the lower ends of themetal interconnects 21 or 37, so as to reduce the capacitance betweenthe interconnects.

[0029] However, the top portions of the air gaps 24 are positioned atsubstantially the same level as the metal interconnects 21 as shown inFIGS. 14B and 14C in the first conventional example and the top portionsof the air gaps 39 are positioned at substantially the same level as themetal interconnects 37 as shown in FIG. 18B in the second conventionalexample. Therefore, the volume of each air gap 24 or 39 is reduced in aregion of the upper interlayer insulating film 23 or 38 between theupper ends of the metal interconnects 21 or 37.

[0030] Accordingly, in the first or second conventional example, sincethe volume of each air gap 24 or 39 is thus reduced in the regionbetween the upper ends of the metal interconnects 21 or 37 where theelectric field is collected, the capacitance between the interconnectscannot be sufficiently reduced. In other words, although the first orsecond conventional example employs the metal interconnect structurehaving an air gap and the portions of the lower interlayer insulatingfilm 11 or 31 between the metal interconnects 21 37 are trenched beforeforming the upper interlayer insulating film 23 or 38 so as to reducethe capacitance between the interconnects, the capacitance between theinterconnects cannot be sufficiently reduced by these conventionaltechniques.

SUMMARY OF THE INVENTION

[0031] In consideration of the aforementioned conventional problem, anobject of the invention is definitely reducing capacitance betweeninterconnects in a semiconductor device having a metal interconnectstructure including an air gap.

[0032] In order to achieve the object, the semiconductor device of thisinvention comprises a plurality of metal interconnects formed on a lowerinterlayer insulating film provided on a semiconductor substrate; and anupper interlayer insulating film covering the plurality of metalinterconnects and having an air gap between the plurality of metalinterconnects, and a top portion of the air gap is positioned at a levelhigher than the plurality of metal interconnects.

[0033] In the semiconductor device of this invention, since the topportion of the air gap is positioned at a level higher than the metalinterconnects, a main portion of the air gap, namely, a portion with arectangular cross-section, is positioned at the same level as the metalinterconnects. Therefore, the volume of the air gap in a region betweenthe upper ends of the metal interconnects where an electric field iscollected can be increased, so as to sufficiently reduce the capacitancebetween the interconnects. As a result, the performance and thereliability of the semiconductor device can be improved.

[0034] In the semiconductor device, it is preferred that portions of thelower interlayer insulating film between the plurality of metalinterconnects are trenched by etching, that a second insulating filmmade from a different material from the lower interlayer insulating filmis formed on the plurality of metal interconnects with a firstinsulating film sandwiched therebetween, and that the lower interlayerinsulating film has an etching rate higher than an etching rate of thesecond insulating film in the etching of the lower interlayer insulatingfilm.

[0035] Since the portions of the lower interlayer insulating filmbetween the plural metal interconnects are thus trenched by the etching,the lower end of the air gap is positioned at a level lower than thelower ends of the metal interconnects, and hence, the volume of the airgap in a region between the lower ends of the metal interconnects wherean electric field is collected can be increased. Therefore, thecapacitance between the interconnects can be further reduced.

[0036] Furthermore, since the second insulating film made from adifferent material from the lower interlayer insulating film and havingan etching rate lower than that of the lower interlayer insulating filmin etching the lower interlayer insulating film is formed on the pluralmetal interconnects with the first insulating film sandwichedtherebetween, no facet is formed in a top portion of the firstinsulating film when the lower interlayer insulating film is etched.Therefore, the upper interlayer insulating film minimally enters theportions between the metal interconnects, and hence, the top portion ofthe air gap can be definitely positioned at a level higher than themetal interconnects.

[0037] In the semiconductor device, it is preferred that the lowerinterlayer insulating film is made from an inorganic insulating materialincluding an inorganic component as a principal constituent andincluding neither nitrogen nor carbon, or a hybrid insulating materialincluding an organic component and an inorganic component, and that thesecond insulating film is made from an inorganic insulating materialincluding an inorganic material as a principal constituent and includingnitrogen or carbon.

[0038] Thus, the lower interlayer insulating film can easily attain anetching rate higher than that of the second insulating film in etchingthe lower interlayer insulating film.

[0039] In the semiconductor device, it is preferred that the lowerinterlayer insulating film is made from an organic insulating materialincluding an organic component as a principal constituent, and that thesecond insulating film is made from an inorganic insulating materialincluding an inorganic component as a principal constituent or a hybridinsulating material including an organic component and an inorganiccomponent.

[0040] Thus, the lower interlayer insulating film can easily attain anetching rate higher than that the second insulating film in etching thelower interlayer insulating film.

[0041] In the semiconductor device, it is preferred that the lowerinterlayer insulating film is made from an inorganic or organic porousinsulating material, and that the second insulating film is made from aninorganic insulating material including an inorganic component as aprincipal constituent or a hybrid insulating material including anorganic component and an inorganic component.

[0042] Thus, the lower interlayer insulating film can easily attain anetching rate higher than that of the second insulating film in etchingthe lower interlayer insulating film.

[0043] The first method for fabricating a semiconductor device of thisinvention comprises the steps of depositing a first metal film on alower interlayer insulating film formed on a semiconductor substrate;forming a second insulating film made from a different material from thelower interlayer insulating film on the first metal film with a firstinsulating film sandwiched therebetween; forming a contact plug openingin the second insulating film and the first insulating film; forming acontact plug by filling the contact plug opening with a second metalfilm; forming a transfer pattern composed of a patterned secondinsulating film, a patterned first insulating film and the contact plugby etching the second insulating film and the first insulating film witha mask pattern formed on the second insulating film in an interconnectpattern used as a mask; forming metal interconnects from the first metalfilm by etching the first metal film with the transfer pattern used as amask; trenching portions of the lower interlayer insulating film betweenthe metal interconnects by etching the lower interlayer insulating filmunder conditions in which the lower interlayer insulating film has anetching rate higher than an etching rate of the second insulating film;and forming an upper interlayer insulating film on the lower interlayerinsulating film, whereby covering the patterned second insulating filmand forming an air gap between the metal interconnects.

[0044] In the first method for fabricating a semiconductor device ofthis invention, the lower interlayer insulating film is etched underconditions in which the etching rate of the lower interlayer insulatingfilm is higher than that of the second insulating film so as to trenchthe portions of the lower interlayer insulating film between the metalinterconnects. Therefore, no facet is formed in a top portion of thefirst insulating film, and hence, the upper interlayer insulating filmminimally enters the portion between the metal interconnects.Accordingly, the top portion of the air gap can be positioned at a levelhigher than the metal interconnects so as to increase the volume of theair gap in a region between the upper ends of the metal interconnectswhere an electric field is collected. As a result, the capacitancebetween the interconnects can be sufficiently reduced.

[0045] The second method for fabricating a semiconductor device of thisinvention comprises the steps of depositing a first metal film on alower interlayer insulating film formed on a semiconductor substrate;forming a second insulating film from a different material from thelower interlayer insulating film on the first metal film with a firstinsulating film sandwiched therebetween; forming a transfer patterncomposed of a patterned second insulating film and a patterned firstinsulating film by etching the second insulating film and the firstinsulating film with a mask pattern formed on the second insulating filmin an interconnect pattern used as a mask; forming metal interconnectsfrom the first metal film by etching the first metal film with thetransfer pattern used as a mask; trenching portions of the lowerinterlayer insulating film between the metal interconnects by etchingthe lower interlayer insulating film under conditions in which the lowerinterlayer insulating film has an etching rate higher than an etchingrate of the second insulating film; and forming an upper interlayerinsulating film on the lower interlayer insulating film, wherebycovering the patterned second insulating film and forming an air gapbetween the metal interconnects.

[0046] In the second method for fabricating a semiconductor device ofthis invention, the lower interlayer insulating film is etched underconditions in which the etching rate of the lower interlayer insulatingfilm is higher than that of the second insulating film so as to trenchthe portions of the lower interlayer insulating film between the metalinterconnects. Therefore, no facet is formed in a top portion of thefirst insulating film, and hence, the upper interlayer insulating filmminimally enters the portion between the metal interconnects.Accordingly, the top portion of the air gap can be positioned at a levelhigher than the metal interconnects so as to increase the volume of theair gap in a region between the upper ends of the metal interconnectswhere an electric field is collected. As a result, the capacitancebetween the interconnects can be sufficiently reduced.

[0047] In the first or second method for fabricating a semiconductordevice, it is preferred that a top portion of the air gap is positionedat a level higher than the metal interconnects.

[0048] Thus, the volume of the air gap in the region between the upperends of the metal interconnects where an electric field is collected canbe definitely increased, resulting in definitely reducing thecapacitance between the interconnects.

[0049] In the first or second method for fabricating a semiconductordevice, it is preferred that the lower interlayer insulating film ismade from an inorganic insulating material including an inorganiccomponent as a principal constituent and including neither nitrogen norcarbon, or a hybrid insulating material including an organic componentand an inorganic component, and that the second insulating film is madefrom an inorganic insulating material including an inorganic material asa principal constituent and including nitrogen or carbon.

[0050] Thus, the lower interlayer insulating film can easily attain anetching rate higher than that of the second insulating film in etchingthe lower interlayer insulating film.

[0051] In the first or second method for fabricating a semiconductordevice, it is preferred that the lower interlayer insulating film ismade from an organic insulating material including an organic componentas a principal constituent, and that the second insulating film is madefrom an inorganic insulating material including an inorganic componentas a principal constituent or a hybrid insulating material including anorganic component and an inorganic component.

[0052] Thus, the lower interlayer insulating film can easily attain anetching rate higher than that of the second insulating film in etchingthe lower interlayer insulating film.

[0053] In the first or second method for fabricating a semiconductordevice, it is preferred that the lower interlayer insulating film ismade from an inorganic or organic porous insulating material, and thatthe second insulating film is made from an inorganic insulating materialincluding an inorganic component as a principal constituent or a hybridinsulating material including an organic component and an inorganiccomponent.

[0054] Thus, the lower interlayer insulating film can easily attain anetching rate higher than that of the second insulating film in etchingthe lower interlayer insulating film.

BRIEF DESCRIPTION OF THE DRAWINGS

[0055]FIGS. 1A, 1B and 1C are cross-sectional views for showingprocedures in a method for fabricating a semiconductor device accordingto Embodiment 1 of the invention;

[0056]FIGS. 2A, 2B and 2C are cross-sectional views for showing otherprocedures in the method for fabricating a semiconductor device ofEmbodiment 1;

[0057]FIGS. 3A, 3B and 3C are cross-sectional views for showing stillother procedures in the method for fabricating a semiconductor device ofEmbodiment 1;

[0058]FIGS. 4A, 4B and 4C are cross-sectional views for showing stillother procedures in the method for fabricating a semiconductor device ofEmbodiment 1;

[0059]FIGS. 5A, 5B and 5C are cross-sectional views for showing stillother procedures in the method for fabricating a semiconductor device ofEmbodiment 1;

[0060]FIG. 6A is a cross-sectional view of a semiconductor deviceaccording to a first or second conventional example and FIG. 6B is across-sectional view of a semiconductor device of Embodiment 1;

[0061]FIGS. 7A, 7B and 7C are cross-sectional views for showingprocedures in a method for fabricating a semiconductor device accordingto Embodiment 2 of the invention;

[0062]FIGS. 8A, 8B and 8C are cross-sectional views for showing otherprocedures in the method for fabricating a semiconductor device ofEmbodiment 2;

[0063]FIGS. 9A, 9B and 9C are cross-sectional views for showing stillother procedures in the method for fabricating a semiconductor device ofEmbodiment 2;

[0064]FIGS. 10A, 10B and 10C are cross-sectional views for showing stillother procedures in the method for fabricating a semiconductor device ofEmbodiment 2;

[0065]FIGS. 11A, 11B and 11C are cross-sectional views for showingprocedures in a method for fabricating a semiconductor device accordingto the first conventional example;

[0066]FIGS. 12A, 12B and 12C are cross-sectional views for showing otherprocedures in the method for fabricating a semiconductor device of thefirst conventional example;

[0067]FIGS. 13A, 13B and 13C are cross-sectional views for showing stillother procedures in the method for fabricating a semiconductor device offirst conventional example;

[0068]FIGS. 14A, 14B and 14C are cross-sectional views for showing stillother procedures in the method for fabricating a semiconductor device ofthe first conventional example;

[0069]FIGS. 15A, 15B and 15C are cross-sectional views for showingprocedures in a method for fabricating a semiconductor device accordingthe second conventional example;

[0070]FIGS. 16A, 16B and 16C are cross-sectional views for showing otherprocedures in the method for fabricating a semiconductor device of thesecond conventional example;

[0071]FIGS. 17A, 17B and 17C are cross-sectional views for showing stillother procedures in the method for fabricating a semiconductor device ofthe second conventional example; and

[0072]FIGS. 18A and 18B are cross-sectional views for showing stillother procedures in the method for fabricating a semiconductor device ofthe second conventional example.

DETAILED DESCRIPTION OF THE INVENTION

[0073] Embodiment 1

[0074] A semiconductor device and a method for fabricating the sameaccording to Embodiment 1 of the invention will now be described withreference to FIGS. 1A through 1C, 2A through 2C, 3A through 3C, 4Athrough 4C and 5A through 5C.

[0075] First, as shown in FIG. 1A, a lower interlayer insulating film101 of an insulating material is formed on a semiconductor substrate 100by CVD or spin coating. Thereafter, although not shown in the drawing, aplug connected to the semiconductor substrate 100 or an interconnectformed on the semiconductor substrate 100 is formed in the lowerinterlayer insulating film 101.

[0076] Next, a first barrier metal layer 102, a first metal film 103 anda second barrier metal layer 104 are successively deposited on the lowerinterlayer insulating film 101. The first barrier metal layer 102 andthe second barrier metal layer 104 are deposited by sputtering and thefirst metal film 103 is formed by the sputtering, CVD or plating. Thefirst metal film 103 may be made from a metal with low resistance suchas aluminum alloy, copper, gold, silver or platinum, and the firstbarrier metal layer 102 and the second barrier metal layer 104 may bemade from a nitride of a metal with a high melting point such astitanium nitride or tantalum nitride.

[0077] Then, as shown in FIG. 1B, a first insulating film 105, a secondinsulating film 106 and a third insulating film 107 are successivelyformed on the second barrier metal layer 104 by the CVD or spin coating.In this case, the second insulating film 106 is made from a differentmaterial from the first insulating film 105, and the third insulatingfilm 107 is made from a different material from the second insulatingfilm 106. Also, the second insulating film 106 is made from aninsulating material having a lower etching rate than the lowerinterlayer insulating film 101 in etching the lower interlayerinsulating film 101. The insulating materials used for the lowerinterlayer insulating film 101, the first insulating film 105, thesecond insulating film 106 and the third insulating film 107 will bedescribed in detail later.

[0078] Next, after forming a first resist pattern 108 on the thirdinsulating film 107 by lithography as shown in FIG. 1C, the thirdinsulating film 107, the second insulating film 106 and the firstinsulating film 105 are dry etched by using the first resist pattern 108as a mask, thereby forming plug openings 109 as shown in FIG. 2A.

[0079] Then, after depositing a second metal film 110 on the thirdinsulating film 107 by the sputtering, CVD or plating as shown in FIG.2B, an unnecessary portion of the second metal film 110 present on thethird insulating film 107 is removed by CMP, thereby forming contactplugs 111 from the second metal film 110 as shown in FIG. 2C.

[0080] Next, after forming a second resist pattern 112 on the thirdinsulating film 107 as shown in FIG. 3A, the third insulating film 107is dry etched by using the second resist pattern 112 as a mask, so as toform a patterned third insulating film 107A in the pattern ofinterconnects as shown in FIG. 3B.

[0081] Then, as shown in FIG. 3C, the second insulating film 106 is dryetched by using the second resist pattern 112 and the patterned thirdinsulating film 107A as a mask, so as to form a patterned secondinsulating film 106A in the pattern of interconnects.

[0082] Subsequently, as shown in FIG. 4A, the first insulating film 105is dry etched by using the second resist pattern 112, the patternedthird insulating film 107A and the patterned second insulating film 106Aas a mask, so as to form a patterned first insulating film 105A in thepattern of interconnects. In this manner, a transfer pattern composed ofthe patterned third insulating film 107A, the patterned secondinsulating film 106A, the patterned first insulating film 105A and thecontact plugs 111 is formed. Thereafter, the second resist pattern 112is removed by ashing as shown in FIG. 4B, and the resultantsemiconductor substrate is cleaned.

[0083] Next, as shown in FIG. 4C, the second barrier metal layer 104,the first metal film 103 and the first barrier metal layer 102 are dryetched by using the transfer pattern as a mask, thereby forming metalinterconnects 113 composed of a patterned second barrier metal layer104A, a patterned first metal film 103A and a patterned first barriermetal layer 102A. In this manner, the patterned third insulating film107A is sputtered, and hence is formed into a third insulating film 107Bhaving facets in top portions thereof.

[0084] Then, as shown in FIG. 5A, the lower interlayer insulating film101 is dry etched under conditions in which the etching rate of thelower interlayer insulating film 101 is higher than the etching rate ofthe second insulating film 106, thereby trenching portions of the lowerinterlayer insulating film 101 between the metal interconnects 113. Inthis etching, although the third insulating film 107B having the facetsin the top portions thereof is removed, the patterned second insulatingfilm 106A and the patterned first insulating film 105A still have arectangular cross-section. In other words, no facets are formed in thetop portions of the patterned second insulating film 106A and thepatterned first insulating film 105A. In this etching, even when thethird insulating film 107B having the facets in the top portions thereofis not completely removed, it is harmless.

[0085] Next, as shown in FIG. 5B, an upper interlayer insulating film114 is formed over the patterned second insulating film 106A, thecontact plugs 111 and the lower interlayer insulating film 101 by theCVD, and air gaps 115 are formed in the upper interlayer insulating film114 between the metal interconnects 113. Since this procedure forforming the upper interlayer insulating film 114 is carried out with nofacets formed in the top portions of the patterned second insulatingfilm 106A and the patterned first insulating film 105A, the upperinterlayer insulating film 114 minimally enters the portions between themetal interconnects 113. Therefore, the top portion of each air gap 115(a portion with a triangular cross-section) is positioned at a levelhigher than the metal interconnect 113.

[0086] Then, as shown in FIG. 5C, the upper interlayer insulating film114 is planarized by the CMP. Thus, an interconnect structure having anair gap is obtained. Thereafter, the aforementioned sequence isrepeated, so as to fabricate a semiconductor device having a multi-layerinterconnect structure.

[0087]FIG. 6A shows the cross-sectional structure of a semiconductordevice according to the first or second conventional example and FIG. 6Bshows the cross-sectional structure of the semiconductor device ofEmbodiment 1.

[0088] As is obvious from FIG. 6A, since the patterned insulating film15A (35A) has the facets in the top portions thereof in thesemiconductor device of the first or second conventional example, theupper interlayer insulating film 22 (38) tends to enter the portionsbetween the metal interconnects 21 (37). Therefore, the height h₁ ofeach air gap 23 (39) composed of a main portion 23 a (39 a) (with arectangular cross-section) and a top portion 23 b (39 b) (with atriangular cross-section) is merely slightly larger than the height h₀of the metal interconnect 21 (37) above the bottom of the air gap.Accordingly, the top portion 23 b (39 b) of the air gap 23 (39) ispositioned at substantially the same level as the metal interconnect 21(39).

[0089] In contrast, as is obvious from FIG. 6B, since no facets areformed in the top portions of the patterned second insulating film 106Aand the patterned first insulating film 105A in the semiconductor deviceof Embodiment 1, the upper interlayer insulating film 114 minimallyenters the portions between the metal interconnects 113. Therefore, theheight h₂ of each air gap 115 composed of a main portion 115 a (with arectangular cross-section) and a top portion 115 b (with a triangularcross-section) is much larger than the height h₀ of the metalinterconnect 113 above the bottom of the air gap. Accordingly, the topportion 115 b of the air gap 115 is positioned at a level higher thanthe metal interconnect 113.

[0090] According to Embodiment 1, since the top portion 115 b of eachair gap 115 is positioned at the level higher than the metalinterconnect 113, the volume of the air gap 115 in a region between theupper ends of the metal interconnects 113 where an electric field iscollected can be increased. As a result, the capacitance between theinterconnects can be sufficiently reduced, so as to improve theperformance and the reliability of the semiconductor device.

[0091] Embodiment 2

[0092] A semiconductor device and a method for fabricating the sameaccording to Embodiment 2 of the invention will now be described withreference to FIGS. 7A through 7C, 8A through 8C, 9A through 9C and 10Athrough 10C.

[0093] First, as shown in FIG. 7A, a lower interlayer insulating film201 of an insulating material is formed on a semiconductor substrate 200by the CVD or spin coating in the same manner as in Embodiment 1.Thereafter, although not shown in the drawing, a plug connected to thesemiconductor substrate 200 or an interconnect formed on thesemiconductor substrate 200 is formed in the lower interlayer insulatingfilm 201. Then, a first barrier metal layer 202, a first metal film 203and a second barrier metal layer 204 are successively deposited on thelower interlayer insulating film 201.

[0094] Next, as shown in FIG. 7B, a first insulating film 205 and asecond insulating film 206 are successively formed on the second barriermetal layer 204 by the CVD or spin coating. In this case, the secondinsulating film 206 is made from a different material from the firstinsulating film 205. Also, the second insulating film 206 is made froman insulating material having a lower etching rate than the lowerinterlayer insulating film 201 in etching the lower interlayerinsulating film 201. The insulating materials used for the lowerinterlayer insulating film 201, the first insulating film 205 and thesecond insulating film 206 will be described in detail later.

[0095] Then, after forming a first resist pattern 207 on the secondinsulating film 206 as shown in FIG. 7C, the second insulating film 206and the first insulating film 205 are dry etched by using the firstresist pattern 207 as a mask, thereby forming a patterned secondinsulating film 206A and a patterned first insulating film 205A both inthe pattern of interconnects as shown in FIG. 8A. Thus, a transferpattern composed of the patterned second insulating film 206A and thepatterned first insulating film 205A is formed. Thereafter, the firstresist pattern 207 is removed by the ashing, and the resultant substrateis cleaned.

[0096] Next, as shown in FIG. 8B, the second barrier metal layer 204,the first metal film 203 and the first barrier metal layer 202 are dryetched by using the transfer pattern as a mask, thereby forming metalinterconnects 208 composed of a patterned second barrier metal layer204A, a patterned first metal film 203A and a patterned first barriermetal layer 202A.

[0097] Then, as shown in FIG. 8C, the lower interlayer insulating film201 is dry etched under conditions in which the etching rate of thelower interlayer insulating film 201 is higher than the etching rate ofthe second insulating film 206, thereby trenching portions of the lowerinterlayer insulating film 201 between the metal interconnects 208. Inthis etching, the patterned second insulating film 206A and thepatterned first insulating film 205A keep their rectangularcross-section, namely, no facets are formed in top portions of thepatterned second insulating film 206A and the patterned first insulatingfilm 205A.

[0098] Subsequently, as shown in FIG. 9A, an upper interlayer insulatingfilm 209 is formed over the metal interconnects 208 and the lowerinterlayer insulating film 201 by the CVD, and air gaps 210 are formedin the upper interlayer insulating film 209 between the metalinterconnects 208. The procedure for forming the upper interlayerinsulating film 209 is carried out with no facets formed in the topportions of the patterned second insulating film 206A and the patternedfirst insulating film 205A. Therefore, the upper interlayer insulatingfilm 209 minimally enters the portions between the metal interconnects208, and hence, a top portion of each air gap 210 (a portion with atriangular cross-section) is positioned at a level higher than the metalinterconnect 208.

[0099] Next, after planarizing the upper interlayer insulating film 209by the CMP as shown in FIG. 9B, a second resist pattern 211 is formed onthe upper interlayer insulating film 209 as shown in FIG. 9C.

[0100] Then, as shown in FIG. 10A, the upper interlayer insulating film209 is dry etched by using the second resist pattern 211 as a mask,thereby forming plug openings 212 in the upper interlayer insulatingfilm 209. Thereafter, the second resist pattern 211 is removed by theashing.

[0101] Next, as shown in FIG. 10B, a second metal film 213 is depositedon the upper interlayer insulating film 209 by the sputtering, CVD orplating so as to fill the plug openings 212.

[0102] Then, as shown in FIG. 10C, an unnecessary portion of the secondmetal film 213 present on the upper interlayer insulating film 209 isremoved by the CMP, so as to form contact plugs 214 from the secondmetal film. Thus, an interconnect structure having an air gap iscompleted. When the aforementioned sequence is repeated, a semiconductordevice having a multi-layer interconnect structure can be fabricated.

[0103] Since the top portion of each air gap 210 is positioned at thelevel higher than the metal interconnects 208 in Embodiment 2, thevolume of the air gap in a region between the upper ends of the metalinterconnects 208 where an electric field is collected can be increased.Therefore, the capacitance between the interconnects can be sufficientlyreduced, resulting in improving the performance and the reliability ofthe semiconductor device.

[0104] (Insulating Materials Used for Lower and Upper InterlayerInsulating Films and First, Second and Third Insulating Films)

[0105] Combinations of insulating materials used for the lowerinterlayer insulating film 101 (201), the upper interlayer insulatingfilm 114 (209), the first insulating film 105 (205), the secondinsulating film 106 (206) of Embodiments 1 and 2 and the thirdinsulating film 107 of Embodiment 1 will now be specifically described.The following description is applicable to both Embodiments 1 and 2unless otherwise mentioned.

[0106] <First Combination>

[0107] In a first combination, the lower interlayer insulating film ismade from an inorganic insulating material including an inorganiccomponent as a principal constituent and including neither nitrogen norcarbon, or a hybrid insulating material including an organic componentand an inorganic component; and the second insulating film is made froman inorganic insulating material including an inorganic component as aprincipal constituent and including nitrogen or carbon.

[0108] Examples of the lower interlayer insulating film are an inorganicinsulating film such as a silicon oxide film or a silicon oxidefluorinated film, and a hybrid insulating film such as a silicon oxidefilm including a hydrogen atom or a hydrocarbon compound like a methylgroup. In this case, the upper interlayer insulating film is also madefrom an inorganic insulating film such as a silicon oxide film or asilicon oxide fluorinated film, or a hybrid insulating film such as asilicon oxide film including a hydrogen atom or a hydrocarbon compoundlike a methyl group.

[0109] An example of the second insulating film is an inorganicinsulating film including nitrogen or carbon, such as a silicon nitridefilm, a silicon oxide nitrided film, a silicon carbide film or a siliconoxide carbonated film.

[0110] When this combination is employed, the etching resistance of thesecond insulating film can be increased in the dry etching of the lowerinterlayer insulating film, and hence, the lower interlayer insulatingfilm can easily attain an etching rate higher than that of the secondinsulating film.

[0111] Examples of the first insulating film are a silicon oxide film, asilicon oxide fluorinated film, a silicon oxide film including ahydrogen atom or a hydrocarbon compound like a methyl group, and what iscalled a low-k film including an organic component as a principalconstituent.

[0112] Also, examples of the third insulating film of Embodiment 1 are asilicon oxide film, a silicon oxide fluorinated film, a silicon oxidefilm including a hydrogen atom or a hydrocarbon compound like a methylgroup, and what is called a low-k film including an organic component asa principal constituent.

[0113] <Second Combination>

[0114] In a second combination, the lower interlayer insulating film ismade from an organic insulating material including an organic componentas a principal constituent; and the second insulating film is made froman inorganic insulating material including an inorganic component as aprincipal constituent or a hybrid insulating material including anorganic component and an inorganic component.

[0115] An example of the lower interlayer insulating film is an organicfilm of an organic polymer such as an aromatic polymer. In this case,the upper interlayer insulating film may be made from an organic film,an inorganic film or a hybrid film. When the upper interlayer insulatingfilm is made from an organic film, a multi-layer interconnect structureincluding a plurality of interconnect structures described in Embodiment1 or 2 can be realized. When the upper interlayer insulating film ismade from an inorganic film or a hybrid film, the film structure can beoptimized in each layer divided by interlayer insulating films.

[0116] Examples of the second insulating film are an inorganicinsulating film such as a silicon oxide film, a silicon oxidefluorinated film, a silicon nitride film, a silicon oxide nitrided film,a silicon carbide film or a silicon oxide carbonated film, and a hybridinsulating film such as a silicon oxide film including a hydrogen atomor a hydrocarbon compound like a methyl group.

[0117] When this combination is employed, the etching resistance of thesecond insulating film can be increased in the dry etching of the lowerinterlayer insulating film. Therefore, the lower interlayer insulatingfilm can easily attain an etching rate higher than that of the secondinsulating film.

[0118] Furthermore, the interlayer insulating film can attain a lowerdielectric constant than in the first combination, and hence, a higherperformance multi-layer interconnect structure with low capacitance canbe realized.

[0119] Examples of the first insulating film are a silicon oxide film, asilicon oxide fluorinated film, a silicon oxide film including ahydrogen atom or a hydrocarbon compound like a methyl group, what iscalled a low-k film including an organic component as a principalconstituent, and what is called a porous film having fine pores.

[0120] Examples of the third insulating film of Embodiment 1 are asilicon oxide film, a silicon oxide fluorinated film, a silicon oxidefilm including a hydrogen atom or a hydrocarbon compound like a methylgroup, what is called a low-k film including an organic component as aprincipal constituent, and what is called a porous film having finepores.

[0121] <Third Combination>

[0122] In a third combination, the lower interlayer insulating film ismade from an inorganic or organic porous insulating material; and thesecond insulating film is made from an inorganic insulating materialincluding an inorganic component as a principal constituent, or a hybridinsulating material including an organic component and an inorganiccomponent.

[0123] An example of the lower interlayer insulating film is aninorganic or organic porous film having fine pores.

[0124] Examples of the second insulating film are an inorganicinsulating film such as a silicon oxide film, a silicon oxidefluorinated film, a silicon nitride film, a silicon oxide nitrided film,a silicon carbide film or a silicon oxide carbonated film, and a hybridinsulating film such as a silicon oxide film including a hydrogen atomor a hydrocarbon compound like a methyl group.

[0125] When this combination is employed, the etching resistance of thesecond insulating film can be increased in the dry etching of the lowerinterlayer insulating film. Therefore, the lower interlayer insulatingfilm can easily attain an etching rate higher than that of the secondinsulating film.

[0126] Furthermore, the interlayer insulating film can attain a lowerdielectric constant than in the first and second combinations, andhence, a much higher performance multi-layer interconnect structure withlow capacitance can be realized.

[0127] Examples of the first insulating film are a silicon oxide film, asilicon oxide fluorinated film, a silicon oxide film including ahydrogen atom or a hydrocarbon compound like a methyl group, what iscalled a low-k film including an organic component as a principalconstituent, and what is called a porous film having fine pores.

[0128] Examples of the third insulating film of Embodiment 1 are asilicon oxide film, a silicon oxide fluorinated film, a silicon oxidefilm including a hydrogen atom or a hydrocarbon compound like a methylgroup, what is called a low-k film including an organic component as aprincipal constituent, and what is called a porous film having finepores.

1. A method for fabricating a semiconductor device comprising the stepsof: depositing a first metal film on a lower interlayer insulating filmformed on a semiconductor substrate; forming a second insulating filmmade from a different material from said lower interlayer insulatingfilm on said first metal film with a first insulating film sandwichedtherebetween; forming a contact plug opening in said second insulatingfilm and said first insulating film; forming a contact plug by fillingsaid contact plug opening with a second metal film; forming a transferpattern composed of a patterned second insulating film, a patternedfirst insulating film and said contact plug by etching said secondinsulating film and said first insulating film with a mask patternformed on said second insulating film in an interconnect pattern used asa mask; forming metal interconnects from said first metal film byetching said first metal film with said transfer pattern used as a mask;trenching portions of said lower interlayer insulating film between saidmetal interconnects by etching said lower interlayer insulating filmunder conditions in which said lower interlayer insulating film has anetching rate higher than an etching rate of said second insulating film;and forming an upper interlayer insulating film on said lower interlayerinsulating film, whereby covering said patterned second insulating filmand forming an air gap between said metal interconnects.
 2. The methodfor fabricating a semiconductor device of claim 1, wherein a top portionof said air gap is positioned at a level higher than said metalinterconnects.
 3. The method for fabricating a semiconductor device ofclaim 1, wherein said lower interlayer insulating film is made from aninorganic insulating material including an inorganic component as aprincipal constituent and including neither nitrogen nor carbon, or ahybrid insulating material including an organic component and aninorganic component, and said second insulating film is made from aninorganic insulating material including an inorganic material as aprincipal constituent and including nitrogen or carbon.
 4. The methodfor fabricating a semiconductor device of claim 1, wherein said lowerinterlayer insulating film is made from an organic insulating materialincluding an organic component as a principal constituent, and saidsecond insulating film is made from an inorganic insulating materialincluding an inorganic component as a principal constituent or a hybridinsulating material including an organic component and an inorganiccomponent.
 5. The method for fabricating a semiconductor device of claim1, wherein said lower interlayer insulating film is made from aninorganic or organic porous insulating material, and said secondinsulating film is made from an inorganic insulating material includingan inorganic component as a principal constituent or a hybrid insulatingmaterial including an organic component and an inorganic component.
 6. Amethod for fabricating a semiconductor device comprising the steps of:depositing a first metal film on a lower interlayer insulating filmformed on a semiconductor substrate; forming a second insulating filmfrom a different material from said lower interlayer insulating film onsaid first metal film with a first insulating film sandwichedtherebetween; forming a transfer pattern composed of a patterned secondinsulating film and a patterned first insulating film by etching saidsecond insulating film and said first insulating film with a maskpattern formed on said second insulating film in an interconnect patternused as a mask; forming metal interconnects from said first metal filmby etching said first metal film with said transfer pattern used as amask; trenching portions of said lower interlayer insulating filmbetween said metal interconnects by etching said lower interlayerinsulating film under conditions in which said lower interlayerinsulating film has an etching rate higher than an etching rate of saidsecond insulating film; and forming an upper interlayer insulating filmon said lower interlayer insulating film, whereby covering saidpatterned second insulating film and forming an air gap between saidmetal interconnects.
 7. The method for fabricating a semiconductordevice of claim 6, wherein a top portion of said air gap is positionedat a level higher than said metal interconnects.
 8. The method forfabricating a semiconductor device of claim 6, wherein said lowerinterlayer insulating film is made from an inorganic insulating materialincluding an inorganic component as a principal constituent andincluding neither nitrogen nor carbon, or a hybrid insulating materialincluding an organic component and an inorganic component, and saidsecond insulating film is made from an inorganic insulating materialincluding an inorganic material as a principal constituent and includingnitrogen or carbon.
 9. The method for fabricating a semiconductor deviceof claim 6, wherein said lower interlayer insulating film is made froman organic insulating material including an organic component as aprincipal constituent, and said second insulating film is made from aninorganic insulating material including an inorganic component as aprincipal constituent or a hybrid insulating material including anorganic component and an inorganic component.
 10. The method forfabricating a semiconductor device of claim 6, wherein said lowerinterlayer insulating film is made from an inorganic or organic porousinsulating material, and said second insulating film is made from aninorganic insulating material including an inorganic component as aprincipal constituent or a hybrid insulating material including anorganic component and an inorganic component.